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TC554001AFI/AFTI/ATRI-70,-85,-10,-70L,-85L,-10L
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT STATIC RAM DESCRIPTION
The TC554001AFI/AFTI/ATRI is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5V 10% power supply. Advanced circuit technology provides both high speed and low power at an operating current of 10 mA/MHz (typ) and a minimum cycle time of 70 ns. It is automatically placed in low-power mode at 2 A standby current (typ) when chip enable ( CE ) is asserted high. There are two control inputs. CE is used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating extreme temperature range of -40 to 85C, the TC554001AFI/AFTI/ATRI can be used in environments exhibiting extreme temperature conditions. The TC554001AFI/AFTI/ATRI is available in a standard plastic 32-pin small-outline package (SOP) and normal and reverse pinout plastic 32-pin thin-small-outline package (TSOP).
FEATURES
* * * * * * * Low-power dissipation Operating: 55 mW/MHz (typical) Single power supply voltage of 5 V 10% Power down features using CE . Data retention supply voltage of 2.0 to 5.5 V Direct TTL compatibility for all inputs and outputs Wide operating temperature range of -40 to 85C Standby Current (maximum):
TC554001AFI/AFTI/ATRI -70,-85,-10 5.5 V 3.0 V 200 A 100 A -70L,-85L,-10L 100 A 50 A
*
Access Times (maximum):
TC554001AFI/AFTI/ATRI -70,-70L Access Time
CE Access Time OE Access Time
-85,-85L 85 ns 85 ns 45 ns
-10,-10L 100 ns 100 ns 50 ns
70 ns 70 ns 35 ns
*
Package: SOP32-P-525-1.27 (AFI) (Weight: 1.14 g typ) TSOP II32-P-400-1.27 (AFTI) (Weight: 0.53 g typ) TSOP II32-P-400-1.27A (ATRI) (Weight: 0.53 g typ)
PIN ASSIGNMENT (TOP VIEW)
32 PIN SOP & TSOP
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD A15 A17 R/W A13 A8 A9 A11 OE A10 CE I/O8 I/O7 I/O6 I/O5 I/O4 VDD A15 A17 R/W A13 A8 A9 A11 OE A10 CE I/O8 I/O7 I/O6 I/O5 I/O4
PIN NAMES
32 PIN TSOP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (ATRI) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND A0~A18 R/W
OE CE
Address Inputs Read/Write Control Output Enable Chip Enable Data Inputs/Outputs Power (+5 V) Ground
I/O1~I/O8 VDD GND
(AFI/AFTI)
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TC554001AFI/AFTI/ATRI-70,-85,-10,-70L,-85L,-10L
BLOCK DIAGRAM
CE A0 A1 A2 A3 A4 A5 A6 A7 A12 A14 A18 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
ROW ADDRESS BUFFER
ROW ADDRESS REGISTER
ROW ADDRESS DECODER
VDD GND MEMORY CELL ARRAY 2,048 x 256 x 8 (4,194,304)
8 DATA CONTROL
SENSE AMP COLUMN ADDRESS DECODER
CLOCK GENERATOR
COLUMN ADDERSS REGISTER COLUMN ADDRESS BUFFER CE A8 A9 A10 A11A13A15A16 A17
OE
R/W
CE
CE
OPERATING MODE
MODE Read Write Output Deselect Standby * = don't care H = logic high L = logic low
CE OE
R/W H L H * Output Input High-Z High-Z
I/O1~I/O8
POWER IDDO IDDO IDDO IDDS
L L L H
L * H *
MAXIMUM RATINGS
SYMBOL VDD VIN VI/O PD Tsolder Tstg Topr Power Supply Voltage Input Voltage Input/Output Voltage Power Dissipation Soldering Temperature (10s) Storage Temperature Operating Temperature RATING VALUE -0.3~7.0 -0.3*~7.0 -0.5~VDD + 0.5 0.6 260 -55~150 -40~85 UNIT V V V W C C C
*: -3.0 V when measured at a pulse width of 50ns
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TC554001AFI/AFTI/ATRI-70,-85,-10,-70L,-85L,-10L
DC RECOMMENDED OPERATING CONDITIONS (Ta = -40 to 85C)
SYMBOL VDD VIH VIL VDH *: PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Data Retention Supply Voltage MIN 4.5 2.4 -0.3* 2.0 TYP 5.0 MAX 5.5 VDD + 0.3 0.6 5.5 UNIT V V V V
-3.0 V when measured at a pulse width of 50 ns
DC CHARACTERISTICS (Ta = -40 to 85C, VDD = 5 V 10%)
SYMBOL IIL IOH IOL ILO PARAMETER Input Leakage Current Output High Current Output Low Current Output Leakage Current VIN = 0 V~VDD VOH = 2.4 V VOL = 0.4 V
CE = VIH or R/W = VIL or OE = VIH, VOUT = 0 V~VDD CE = VIL and R/W = VIH, IOUT = 0 mA, Other Input = VIH/VIL CE = 0.2 V and R/W = VDD - 0.2 V, IOUT = 0 mA, Other Input = VDD - 0.2 V/0.2 V CE = VIH
TEST CONDITION
MIN -1.0 2.1
TYP 15 10 2 2
MAX 1.0 1.0 70
UNIT A mA mA A
tcycle = MIN tcycle = 1 s tcycle = MIN tcycle = 1 s
lDDO1 Operating Current lDDO2
mA 60 mA 3 200 5 100 A mA
IDDS1
-70,-85,-10 Standby Current IDDS2
CE = VDD - 0.2 V, VDD = 2.0 V~5.5 V
Ta = 25C Ta = -40~85C Ta = 25C Ta = -40~85C

-70L,-85L,-10L
CAPACITANCE (Ta = 25C, f = 1 MHz)
SYMBOL CIN COUT Note: PARAMETER Input Capacitance Output Capacitance VIN = GND VOUT = GND TEST CONDITION MAX 10 10 UNIT pF pF
This parameter is periodically sampled and is not 100% tested.
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TC554001AFI/AFTI/ATRI-70,-85,-10,-70L,-85L,-10L
AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = -40 to 85C, VDD = 5 V 10%)
READ CYCLE
TC554001AFI/AFTI/ATRI SYMBOL PARAMETER -70,-70L MIN tRC tACC tCO tOE tCOE tOEE tOD tODO tOH Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Output Data Hold Time 70 5 0 10 MAX 70 70 35 30 30 -85,-85L MIN 85 5 0 10 MAX 85 85 45 35 35 -10,-10L MIN 100 5 0 10 MAX 100 100 50 40 40 ns UNIT
WRITE CYCLE
TC554001AFI/AFTI/ATRI SYMBOL PARAMETER -70,-70L MIN tWC tWP tCW tAS tWR tODW tOEW tDS tDH Write Cycle Time Write Pulse Width Chip Enable to End of Write Address Setup Time Write Recovery Time R/W Low to Output High-Z R/W High to Output Active Data Setup Time Data Hold Time 70 50 60 0 0 0 30 0 MAX 30 -85,-85L MIN 85 55 70 0 0 0 35 0 MAX 35 -10,-10L MIN 100 60 80 0 0 0 40 0 MAX 40 ns UNIT
AC TEST CONDITIONS
PARAMETER Output load Input pulse level Timing measurements Reference level t R, t F TEST CONDITION 100 pF + 1 TTL Gate 0.4 V, 2.6 V 1.5 V 1.5 V 5 ns
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TC554001AFI/AFTI/ATRI-70,-85,-10,-70L,-85L,-10L
TIMING DIAGRAMS
READ CYCLE
(See Note 1)
tRC Address tACC tCO
CE
tOH
tOE
OE
tOD
tOEE tCOE DOUT Hi-Z VALID DATA OUT
tODO Hi-Z
WRITE CYCLE 1 (R/W CONTROLLED)
(See Note 4)
tWC Address tAS R/W tCW
CE
tWP
tWR
tODW DOUT (See Note 2) Hi-Z tDS DIN (See Note 5)
tOEW (See Note 3) tDH (See Note 5)
VALID DATA IN
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TC554001AFI/AFTI/ATRI-70,-85,-10,-70L,-85L,-10L
WRITE CYCLE 2 (CE CONTROLLED)
(See Note 4)
tWC Address tAS R/W tCW
CE
tWP
tWR
tCOE DOUT Hi-Z
tODW Hi-Z tDS tDH (See Note 5)
DIN
(See Note 5)
VALID DATA IN
Note: (1) (2) (3) (4) (5)
R/W remains HIGH for the read cycle. If CE goes LOW coincident with or after R/W goes LOW, the outputs will remain at high impedance. If CE goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at high impedance. If OE is HIGH during the write cycle, the outputs will remain at high impedance. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied.
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TC554001AFI/AFTI/ATRI-70,-85,-10,-70L,-85L,-10L
DATA RETENTION CHARACTERISTICS (Ta = -40 to 85C)
SYMBOL VDH PARAMETER Data Retention Supply Voltage -70,-85,-10 IDDS2 Standby Current -70L,-85L,-10L tCDR tR *: VDH = 3.0 V VDH = 5.5 V VDH = 3.0 V VDH = 5.5 V MIN 2.0 0 5 TYP MAX 5.5 100 200 50* 100 ns ms A UNIT V
Chip Deselect to Data Retention Mode Time Recovery Time
5 A (max) at Ta = -40 to 40C
CE CONTROLLED DATA RETENTION MODE
VDD
DATA RETENTION MODE
4.5 V
(See Note) VIH tCDR
CE
(See Note) tR
VDD - 0.2 V
GND
Note: When CE is operating at the VIH level (2.4V), the standby current is given by IDDS1 during the transition of VDD from 4.5 to 2.6V.
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TC554001AFI/AFTI/ATRI-70,-85,-10,-70L,-85L,-10L
PACKAGE DIMENSIONS
Weight: 1.14 g (typ)
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PACKAGE DIMENSIONS
Weight: 0.53 g (typ)
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TC554001AFI/AFTI/ATRI-70,-85,-10,-70L,-85L,-10L
PACKAGE DIMENSIONS
Weight: 0.53 g (typ)
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RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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